Methods for forming a germanium island using selective epitaxial growth and a sacrificial filling layer

ABSTRACT

A method for obtaining a semiconductor island includes epitaxially growing a semiconductor structure over a substrate with a mask layer defining a region not covered by the mask layer. The semiconductor structure includes a first portion located adjacent to the mask layer and a second portion located away from the mask layer. The first portion has a first height that is less than a second height of a portion of the mask layer located adjacent to the first portion. The second portion has a third height that is equal to, or greater than the second height. The method also includes forming a filling layer over at least the first portion; and, subsequently removing at least a portion of the semiconductor structure that is located above the second height. Devices made by this method are also disclosed.

GOVERNMENT LICENSE RIGHTS

This work was partially supported by Korea Institute of Planning andEvaluation for Technology in Food, Agriculture, Forestry (IPET) throughHigh Value-added Food Technology Development Program, funded by Ministryof Agriculture, Food and Rural Affairs (MAFRA) (award no. 117062-3), theInstitute for Information & communications Technology Promotion (IITP),funded by the Korea government (MSIT) (award no. 2016-0-00080), and theU.S. National Science Foundation (NSF) Small Business InnovationResearch (SBIR) (award no. 1534793). The governments have certain rightsin the invention.

TECHNICAL FIELD

This application relates generally to methods for manufacturingsemiconductor devices. More particularly, the disclosed embodimentsrelate to methods for obtaining planarized semiconductor islands.

BACKGROUND

Epitaxial growth is a popular method of creating a crystalline region ona semiconductor substrate. However, formation of semiconductorstructures in unwanted regions of the semiconductor substrate isundesirable.

Selective epitaxial growth (SEG) is used for creating a crystallineregion on targeted areas of the semiconductor substrate. For a selectiveepitaxial growth, a semiconductor substrate is covered with a maskingmaterial, exposing certain areas of the underlying substrate. For suchsemiconductor substrate, the epitaxial growth occurs mainly on theexposed areas of the semiconductor substrate, and less so on the maskingmaterial.

However, certain semiconductor materials, when epitaxially grown, formnon-flat top surfaces. On the other hand, many semiconductor devicesrequire a flat surface to build additional semiconductor structuresthereon, which, in turn, requires additional operations to planarize thesemiconductor structures with non-flat top surfaces. Such additionaloperations can be time-consuming and costly, and may cause damages tothe semiconductor structures.

SUMMARY

Thus, there is a need for improved methods of obtaining epitaxiallygrown semiconductor structures with planar top surfaces. A number ofembodiments that overcome the limitations and disadvantages describedabove are presented in more detail below. These embodiments provideimproved methods for making such semiconductor structures and devicesthat include such semiconductor structures. Such improved methods wouldalso enable a faster process in obtaining epitaxially grownsemiconductor structures with planar top surfaces while reducing damagescaused by planarization operations, thereby increasing the yield inmaking devices with such semiconductor structures.

As described in more detail below, some embodiments involve a method forobtaining a semiconductor island. The method includes epitaxiallygrowing one or more semiconductor structures over a substrate with oneor more mask layers defining one or more regions that are not covered bythe one or more mask layers over the substrate. The one or moresemiconductor structures are epitaxially grown over the one or moreregions that are not covered by the one or more mask layers. Arespective epitaxially grown semiconductor structure of the one or moreepitaxially grown semiconductor structures includes a first portionlocated adjacent to the one or more mask layers and a second portionlocated away from the one or more mask layers. The first portion of therespective epitaxially grown semiconductor structure has a height thatis less than a height of a portion of the one or more mask layerslocated adjacent to the first portion of the respective epitaxiallygrown semiconductor structure. The second portion of the respectiveepitaxially grown semiconductor structure has a height that is equal to,or greater than, the height of the portion of the one or more masklayers located adjacent to the first portion of the respectiveepitaxially grown semiconductor structure. The method also includesforming one or more filling layers over at least the first portion ofthe respective epitaxially grown semiconductor structure; and,subsequent to forming the one or more filling layers over at least thefirst portion of the respective epitaxially grown semiconductorstructure, removing at least a portion of the respective epitaxiallygrown semiconductor structure that is located above the height of theportion of the one or more mask layers located adjacent to the firstportion of the respective epitaxially grown semiconductor structure.

In accordance with some embodiments, a semiconductor device includessubstrate and one or more semiconductor layers defining one or moreregions that are not covered by the one or more semiconductor layersover the substrate. The one or more semiconductor layers includesilicon. The semiconductor device also includes one or moresemiconductor structures located over the one or more regions that arenot covered by the one or more semiconductor layers. The one or moresemiconductor structures includes germanium. A respective semiconductorstructure of the one or more semiconductor structures includes a firstportion located adjacent to the one or more semiconductor layers and asecond portion located away from the one or more semiconductor layers.The first portion of the respective semiconductor structure has a heightthat is less than a height of a portion of the one or more semiconductorlayers located adjacent to the first portion of the respectivesemiconductor structure. The second portion of the respectivesemiconductor structure has a height that is equal to, or greater than,the height of the portion of the one or more semiconductor layerslocated adjacent to the first portion of the respective semiconductorstructure. The semiconductor device further includes one or more fillinglayers located over at least the first portion of the respectivesemiconductor structure.

In accordance with some embodiments, a semiconductor device includes asubstrate and one or more first semiconductor structures located overthe substrate. A respective first semiconductor structure of the one ormore first semiconductor structures has a substantially flat topsurface, a substantially vertical side surface, and a diagonal surfaceextending from the top surface to the side surface. The diagonal surfaceis non-parallel and non-perpendicular to the top surface andnon-parallel and non-perpendicular to the side surface. Thesemiconductor device also includes one or more second semiconductorstructures. A respective second semiconductor structure of the one ormore second semiconductor structures is located on the diagonal surfaceof a corresponding first semiconductor structure of the one or morefirst semiconductor structures. The respective second semiconductorstructure has a side surface aligned with the side surface of thecorresponding first semiconductor structure and a top surface alignedwith the top surface of the corresponding first semiconductor structure.

In accordance with some embodiments, a semiconductor device is made byany method described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the aforementioned aspects as well asadditional aspects and embodiments thereof, reference should be made tothe Description of Embodiments below, in conjunction with the followingdrawings.

FIGS. 1A-1D are partial cross-sectional views of a semiconductorsubstrate, illustrating a method of obtaining a semiconductor island inaccordance with some embodiments.

FIG. 1E is an example scanning electron microscope image of across-section of a semiconductor substrate with an epitaxially growngermanium island.

FIGS. 2A and 2B are scanning electron microscope images of across-section of a semiconductor substrate with a planarized germaniumisland in accordance with some embodiments.

FIGS. 3A-3G are partial cross-sectional views of a semiconductorsubstrate, illustrating a method of obtaining a semiconductor island inaccordance with some embodiments.

FIGS. 4A and 4B are scanning electron microscope images ofcross-sections of semiconductor substrates processed with at least someof the operations shown in FIGS. 3A-3G in accordance with someembodiments.

FIGS. 5A-5D are partial cross-sectional views of a semiconductorsubstrate, illustrating a method of obtaining semiconductor islands inaccordance with some embodiments.

FIGS. 6A-6F are partial cross-sectional views of semiconductorsubstrates with semiconductor devices in accordance with someembodiments.

FIGS. 7A-7C are flow diagrams illustrating a method of obtaining asemiconductor island in accordance with some embodiments.

Like reference numerals refer to corresponding parts throughout thefigures.

Unless noted otherwise, the figures are not drawn to scale.

DESCRIPTION OF EMBODIMENTS

As explained above, selective epitaxial growth (SEG) can be used forcreating a crystalline region on targeted areas of the semiconductorsubstrate. However, certain semiconductor materials, such as germanium,when epitaxially grown, form a pyramid shaped structure. This is becausethe speed of the germanium growth has a very high dependency on thecrystalline direction. In many cases, germanium grows faster in thefirst dominant direction (100) than the second dominant direction (311).This discrepancy of the growth speed leads to a germanium island havinga pyramid shape. This pyramid-shaped germanium island is unsuitable formany semiconductor applications, which require a flat surface forfabricating additional semiconductor structures thereon. Without a flatsurface, both the performance and the yield of a semiconductor devicethat includes the pyramid-shaped germanium island are severely impaired.

In addition, although a planarization operation, such as achemical-mechanical-planarization process, can be used to remove aportion of the pyramid-shaped germanium island to provide a germaniumisland with a flat top surface, the pyramid-shaped germanium island canhave a height over a micrometer, which is time-consuming and costly toplanarize. Furthermore, such extensive planarization operation can causedamages (e.g., cracks or breakage) in the germanium island and/oradjacent structures.

Underfilling regions selected for selective epitaxial growth (e.g.,regions not covered by a mask layer) with the epitaxially growngermanium island can lower the height of the pyramid-shaped germaniumisland, which requires less time spent on planarization operations.However, if the epitaxially grown germanium island is located entirelybelow the top surface of the mask layer, forming electrical contactswith the epitaxially grown germanium island can add challenges. Inaddition, the epitaxially grown germanium, due to the sloped facets, hasa flat region that is substantially less than (e.g., less than 80%) theentire top surface, which, in turn, leads to additional challenges. Ifthe epitaxially grown germanium island is located at least partiallyabove the top surface of the mask layer, planarization is often requiredto level the top surface of the germanium island to the top surface ofthe mask layer. However, planarizing an underfilled semiconductor islandcan cause damages to the semiconductor island. In addition, theplanarization operation on an underfilled semiconductor island canincrease the gap between the semiconductor island and the mask layer,which changes or impairs the performance of a semiconductor device thatincludes the semiconductor island. For example, an electrical contactformed over the increased gap may be more susceptible to a mechanicalforce (e.g., due to a thermal expansion and/or shrinking, an externalshock, etc.) and may break more easily.

Methods that address the above problems are described herein. Because asemiconductor structure is epitaxially grown without overfilling aregion selected for selective epitaxial growth, the height of theepitaxially grown semiconductor structure is lower than the height of asemiconductor structure epitaxially grown to overfill the region. Thisreduces the amount of semiconductor material that needs to be removedduring the planarization operation. In addition, a sacrificial layer isused to provide mechanical support to the epitaxially grownsemiconductor structure, which preserves the integrity of thesemiconductor structure and reduces damages during the planarizationoperation. Thus, the disclosed methods enable faster and more costeffective ways to provide epitaxially grown semiconductor structures(e.g., germanium structures) at a high yield.

Reference will be made to certain embodiments, examples of which areillustrated in the accompanying drawings. While the underlyingprinciples will be described in conjunction with the embodiments, itwill be understood that it is not intended to limit the scope of claimsto these particular embodiments alone. On the contrary, the claims areintended to cover alternatives, modifications and equivalents that arewithin the scope of the claims.

Moreover, in the following description, numerous specific details areset forth to provide a thorough understanding of the present invention.However, it will be apparent to one of ordinary skill in the art thatthe invention may be practiced without these particular details. Inother instances, methods, procedures, components, and networks that arewell-known to those of ordinary skill in the art are not described indetail to avoid obscuring aspects of the underlying principles.

It will also be understood that, although the terms first, second, etc.may be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are only used to distinguishone element from another. For example, a first group could be termed asecond group, and, similarly, a second group could be termed a firstgroup, without departing from the scope of the claims. The first groupand the second group are both groups (e.g., of semiconductorstructures), but they are not the same group.

The terminology used in the description of the embodiments herein is forthe purpose of describing particular embodiments only and is notintended to limiting of the scope of claims. As used in the descriptionand the appended claims, the singular forms “a,” “an,” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will also be understood that the term “and/or”as used herein refers to and encompasses any and all possiblecombinations of one or more of the associated listed items. It will befurther understood that the terms “comprises” and/or “comprising,” whenused in this specification, specify the presence of stated features,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,integers, steps, operations, elements, components, and/or groupsthereof.

FIGS. 1A-1D are partial cross-sectional views of a semiconductorsubstrate, illustrating a method of obtaining a semiconductor island inaccordance with some embodiments.

FIG. 1A illustrates a substrate 102 and a mask layer 104 on thesubstrate 102. Although the substrate 102 is shown as a wafer in FIGS.1A-1D, 3A-3G, and 5A-5D, the substrate 102 may include additionalfeatures not shown in FIGS. 1A-1D, 3A-3G, and 5A-5D. In someembodiments, the substrate 102 includes silicon devices (e.g., siliconcomplementary metal-oxide-semiconductor devices as well as any otherstructures typically formed during the front-end of the line (FEOL)processes). In some embodiments, the substrate 102 includes an oxidelayer on the silicon devices (e.g., FIGS. 6A-6F).

In some embodiments, the mask layer 104 includes a dielectric material(e.g., silicon dioxide, germanium dioxide, etc.). In some embodiments,the mask layer 104 is made of (or consists of) a dielectric material(e.g., silicon dioxide, germanium dioxide, etc.). The mask layer 104exposes one or more portions of the substrate 102. In some embodiments,the mask layer 104 (e.g., the dielectric material) is deposited on thesubstrate 102 and subsequently etched to expose the one or more portions(or regions) of the substrate 102 (e.g., for subsequent epitaxial growthover the exposed portions or regions). In some embodiments, thesubstrate 102 is further etched. In some cases, this further etchingprovides a surface more suitable for epitaxial growth.

FIG. 1B illustrates that a semiconductor structure 106 (e.g., agermanium island) is epitaxially grown. The conditions (e.g., pressure,temperature, and chemical composition) for epitaxial growth of germaniumare well known, and thus, are omitted herein for brevity. In someembodiments, the methods described herein do not require the use of anetchant (e.g., HCl gas) to suppress growth of semiconductor structureson the mask layer 104 during the epitaxial growth, although the use ofan etchant is not precluded. In some embodiments, the methods includeusing an etchant during the epitaxial growth. The conditions forepitaxial growth can be adjusted to obtain the desired growth profile.Thus, it is possible to customize the shape of the epitaxially grownsemiconductor structures. In some embodiments, the epitaxial growth isperformed at a temperature between 350 and 650° C. In some embodiments,the epitaxial growth is performed at a pressure between 20 Torr and 150Torr.

FIG. 1C illustrates that the semiconductor structure 106 continues togrow. FIG. 1C also illustrates that the semiconductor structure 106 hascompletely filled the region defined by the mask layer 104 (e.g., theopening in the mask layer 104). The semiconductor structure 106 in FIG.1C has a pyramid-like shape at a level above the mask layer 104 (e.g.,the semiconductor structure 106 has sloped top surfaces that meet at anapex). FIG. 1E is an example scanning electron microscope (SEM) image ofa cross-section of a semiconductor substrate with an overgrown germaniumisland formed by epitaxial growth.

FIG. 1D illustrates that the semiconductor structure 106 is planarized(e.g., using a chemical-mechanical-planarization operation) so that thetop surface of the semiconductor structure 106 is level with the topsurface of the mask layer 104. However, this requires a significantequipment time to remove the entire portion of the pyramid-shapedsemiconductor structure 106 that is located above the top surface of themask layer 104.

FIG. 2A is a scanning electron microscope image of a cross-section of asemiconductor substrate with a planarized germanium island in accordancewith some embodiments. FIG. 2B is an enlarged view of the image shown inFIG. 2A.

As shown in FIG. 2A, even after the planarization operation (e.g., thechemical-mechanical-planarization), the top surface of the semiconductorstructure is not flat (e.g., curved).

In addition, as shown in FIG. 2B, the planarization operation hasincreased the gap between the semiconductor structure and the masklayer. After the planarization operation, the distance d₀ between thesemiconductor structure and the mask layer on a plane located on top ofthe mask layer is greater than a distance (e.g., the distance d₁ shownin FIG. 3D) between the semiconductor structure and the mask layer onthe plane located on top of the mask layer. Without limiting the scopeof claims, it is believed that the planarization operation causesrounding of the portion of the semiconductor structure near the masklayer, which, in turn, increases the distance between the semiconductorstructure and the mask layer.

FIGS. 3A-3G are partial cross-sectional views of a semiconductorsubstrate, illustrating a method of obtaining a semiconductor island inaccordance with some embodiments.

The processes illustrated in FIGS. 3A and 3B are similar to thoseillustrated in FIGS. 1A and 1B. For brevity, the description of thesefigures is not repeated herein.

Although now shown in FIG. 3A (or FIG. 1A), one or more additionallayers (e.g., a silicon oxide layer) are located on the substrate 102prior to epitaxial growth of the semiconductor structure 306 tofacilitate the hetero-epitaxial growth (e.g., epitaxial growth ofgermanium over a silicon substrate) and suppress defects from thelattice mismatch. In some cases, the one or more additional layers aredeposited on the substrate 102 before the mask layer 104 is placed overthe substrate 102. In some embodiments, the one or more additionallayers are formed on the substrate 102 after the mask layer 104 isplaced over the substrate 102.

Also, although not shown in FIG. 3B (or FIG. 1B), additionalsemiconductor structures (e.g., particles, which are also called nuclei)are sometimes formed on the mask layer 104 during the epitaxial growthof the semiconductor structure 306. Such additional semiconductorstructures often interfere with, or lowers, the performance ofsemiconductor devices that include the semiconductor structure 306. Insome embodiments, such additional semiconductor structures are removedby the operations described in U.S. patent application Ser. No.15/051,362, filed Feb. 23, 2016, which is incorporated by referenceherein in its entirety. For brevity, the description of such operationsis not repeated herein.

FIG. 3C illustrates that the semiconductor structure 306 continues togrow. In FIG. 3C, the semiconductor structure 306 does not fill theopening defined by the mask layer 104. In particular, the semiconductorstructure 306 includes a first portion 312 that is located adjacent tothe mask layer 104 (e.g., in some cases, the first portion 312 is incontact with the mask layer 104). The first portion 312 of thesemiconductor structure 306 has a height h₁ that is less than a heighth₃ of a portion of the mask layer 104 located adjacent to the firstportion 312 of the semiconductor structure 306 (e.g., in some cases, theportion of the mask layer 104 located adjacent to the first portion 312of the semiconductor structure 306 is in contact with the first portion312 of the semiconductor structure 306).

At the same time, the semiconductor structure 306 has a second portion314 (e.g., a horizontally-central vertical portion of the semiconductorstructure 306) that is located away from the mask layer 104. The secondportion 314 of the semiconductor structure 306 has a height h₂ that isequal to, or greater than, the height h₃ of the portion of the masklayer 104 located adjacent to the first portion 312 of the semiconductorstructure 306. This facilitates forming additional semiconductor devicesand/or electrical contacts over the semiconductor structure 306, evenafter the semiconductor structure 306 is planarized.

FIG. 3D illustrates that a filling layer 308 is formed over thesemiconductor structure 306. In some embodiments, the filling layer 308is a continuous layer. In some embodiments, the filling layer 308 isformed over the semiconductor structure 306 and the mask layer 104. Insome embodiments, the filling layer 308 includes a dielectric material,such as oxide or nitride (e.g., silicon dioxide, silicon nitride,germanium oxide, or germanium nitride), or a polycrystalline oramorphous semiconductor material, such as polysilicon or poly-germanium.In some embodiments, the filling layer 308 is made of a material (e.g.,polysilicon) that allows conformal deposition so that the filling layer308 can fill the sharp crevice between the mask layer 104 and thesemiconductor structure 306.

FIG. 3D also indicates that the semiconductor structure 306 has adistance d₁ to the mask layer 104 along a plane located at the height ofthe mask layer 104 (e.g., the plane is located on the top surface of themask layer 104).

FIG. 3E illustrates that a portion of the filling layer 308 and aportion of the semiconductor structure 306 are removed (e.g., using aplanarization operation, such as chemical-mechanical-planarization).

FIG. 3F illustrates that an additional portion of the filling layer 308and an additional portion of the semiconductor structure 306 are removed(e.g., using a planarization operation, such aschemical-mechanical-planarization). In some embodiments, one or moreportions of the mask layer 104 are also removed during the planarizationoperation.

FIG. 3F shows that the top surface of the semiconductor structure 306 isplanar, and level with the top surface of the mask layer 104. Inaddition, the filling layer 308 prevented or reduced rounding of thesloped facet of the semiconductor structure 306. Thus, the semiconductorstructure 306 shown in FIG. 3F has a distance d₂ to the mask layer 104along the plane located at the height of the mask layer 104, and thedistance d₂ corresponds substantially to distance d₁ (e.g., the distanced₁ is at least 80% of the distance d₂, or in some cases, at least 90%,95%, 96%, 97%, 98%, 99%, 99.5%, or 99.9% of the distance d₂).

FIG. 3G illustrates that, in some cases, the mask layer 104 is removed(e.g., using an etching operation, such as a wet etch or a dry etch,that is specific to the material of the mask layer 104, such as anoxide).

FIGS. 4A and 4B are scanning electron microscope images ofcross-sections of semiconductor substrates processed with at least someof the operations shown in FIGS. 3A-3G in accordance with someembodiments.

FIG. 4A shows a cross-section of a semiconductor substrate withgermanium islands on a silicon substrate, where the germanium islandsare separated by an oxide layer (similar to the cross-sectionillustrated in FIG. 3F).

FIG. 4B shows a cross-section of a semiconductor substrate withgermanium islands on a silicon substrate, where the oxide layer has beenremoved (similar to the cross-section illustrated in FIG. 3G).

FIGS. 5A-5D clarify that the operations illustrated in FIGS. 3A-3G canbe performed in forming multiple semiconductor structures (e.g.,germanium islands) on a single semiconductor substrate.

FIG. 5A illustrates that semiconductor structures 306 are epitaxiallygrown to a preselected height. FIG. 5B illustrates that a filling layer308 is applied on the semiconductor structures 306. FIG. 5C illustratesthat a portion of the filling layer 308 and portions of thesemiconductor structures 306 are removed (e.g., bychemical-mechanical-planarization). FIG. 5D illustrates that the masklayer 104 is removed (e.g., etched).

Certain other features described with respect to FIGS. 3A-3G can beapplied analogously to the processes illustrated in FIGS. 5A-5D. Forbrevity, such details are not repeated herein.

FIGS. 6A-6F are partial cross-sectional views of semiconductorsubstrates with semiconductor devices in accordance with someembodiments.

FIG. 6A illustrates that the substrate 102 includes complementarymetal-oxide-semiconductor (CMOS) devices with source/drains 602 andgates 604. In FIG. 6A, a mask layer 606 (e.g., silicon dioxide) isformed on the substrate 102. In some embodiments, the mask layer 606includes silicon dioxide of at least 2 μm thickness, for growing agermanium layer thereon. This particular thickness range for the silicondioxide was found to improve the quality of the crystallinity of theepitaxially grown germanium.

The complementary metal oxide-semiconductor devices shown in FIG. 6Aincludes a PMOS transistor (e.g., ametal-oxide-semiconductor-field-effect transistor having a body in an nregion and the source and drain in p+ regions) and an NMOS transistor(e.g., a metal-oxide-semiconductor-field-effect transistor having a bodyin a p region and the source and drain in n+ regions).

In some cases, the substrate 102 is a p-doped substrate and a portion ofthe substrate 102 is doped to form an n-well 603. Portions of the n-well603 are doped (with p-type dopants) to form the source and drain of aPMOS transistor. Optionally, a portion of the substrate 102 is furtherdoped (with p-type dopants) to form a p-well 605. Portions of the p-well605 are doped (with n-type dopants) to form the source and drain of anNMOS transistor. Alternatively, portions of the p-doped substrate aredoped (with n-type dopants), without further doping the p-dopedsubstrate with p-type dopants, to form the source and drain of an NMOStransistor.

In some cases, the substrate 102 is a n-doped substrate and a portion ofthe substrate 102 is doped to form an p-well 603. Portions of the p-well603 are doped (with n-type dopants) to form the source and drain of aNMOS transistor. Optionally, a portion of the substrate 102 is furtherdoped (with n-type dopants) to form a n-well 605. Portions of the n-well605 are doped (with p-type dopants) to form the source and drain of anPMOS transistor. Alternatively, portions of the n-doped substrate aredoped (with p-type dopants), without further doping the n-dopedsubstrate with n-type dopants, to form the source and drain of an PMOStransistor.

FIG. 6B illustrates that a semiconductor structure 608 (e.g., germanium)is formed using the processes described above with respect to FIGS.3A-3F and 5A-5C.

FIG. 6C illustrates that an additional structure 610 (e.g., a metal orsemiconductor wire) is formed over the semiconductor structure 608.

FIG. 6D is similar to FIG. 6C, except that the semiconductor structure608 and a source or a drain of a transistor are electrically coupled(directly as shown in FIG. 6D or indirectly through one or moreelectrical wires, such as polysilicon wires). As shown in FIG. 6D, insome cases, the semiconductor structure 608 is formed (e.g., viaepitaxial growth) directly on a substrate. In some embodiments, thesemiconductor structure 608 is formed (e.g., via epitaxial growth)directly on a doped portion of the substrate, as shown in FIG. 6D.

FIG. 6E illustrates that a deep well 615 is formed in the substrate 102.In some cases, at least a portion of the deep well 615 is furtherlowered by formation of one or more layers 617 of an oxide (e.g., asilicon dioxide) over the deep well 615. In some embodiments, thesemiconductor structure 608 is formed to extend down to the deep well615.

FIG. 6F illustrates that at least a portion of the semiconductorstructure 608 is doped (e.g., with n-type or p-type dopants) to form afloating well 612, and the source and drain regions 614 within thefloating well 612. FIG. 6F also illustrates that a gate region is formedover the floating well 612, one or more additional protective layers(e.g., an oxide layer) are deposited over the floating well 612 with thesource and drain regions 612 and the gate region and the mask layer 606.FIG. 6F further illustrates that one or more additional structures 616(e.g., metal or semiconductor wires) are formed over the one or moreadditional protective layers.

FIGS. 7A-7C are flow diagrams illustrating method 700 of obtaining asemiconductor island in accordance with some embodiments.

The method includes epitaxially growing (702) one or more semiconductorstructures over a substrate with one or more mask layers defining one ormore regions that are not covered by the one or more mask layers overthe substrate (e.g., FIGS. 3A-3C). The one or more semiconductorstructures are epitaxially grown over the one or more regions that arenot covered by the one or more mask layers. A respective epitaxiallygrown semiconductor structure of the one or more epitaxially grownsemiconductor structures includes a first portion (e.g., the firstportion 312 in FIG. 3C) located adjacent to the one or more mask layers(e.g., the first portion is in contact with the one or more mask layersor is within 1 μm of the one or more mask layers) and a second portion(e.g., the second portion 314 in FIG. 3C) located away from (e.g., thesecond portion is located at least 1 μm away from the one or more masklayers) the one or more mask layers (e.g., the first portion 312 and thesecond portion 314 in FIG. 3C). The first portion of the respectiveepitaxially grown semiconductor structure has a height (e.g., the heighth₁ in FIG. 3C) that is less than a height (e.g., the height h₃ in FIG.3C) of a portion of the one or more mask layers located adjacent to thefirst portion of the respective epitaxially grown semiconductorstructure. The second portion of the respective epitaxially grownsemiconductor structure has a height (e.g., the height h₂ in FIG. 3C)that is equal to, or greater than, the height of the portion of the oneor more mask layers located adjacent to the first portion of therespective epitaxially grown semiconductor structure.

In some embodiments, the one or more epitaxially grown semiconductorstructures include (704) germanium. In some embodiments, the one or moreepitaxially grown semiconductor structures consist of germanium. In someembodiments, the one or more epitaxially grown semiconductor structuresinclude germanium, but they do not consist of germanium (e.g., the oneor more epitaxially grown semiconductor structures also include amaterial that is not germanium).

In some embodiments, the one or more mask layers include (706)dielectric material (e.g., silicon dioxide, germanium dioxide, etc.).

In some embodiments, the one or more semiconductor structures are formed(708) in a single epitaxial growth process.

In some embodiments, the substrate includes (710) a plurality ofsemiconductor devices thereon (e.g., transistors as shown in FIG. 6A).

In some embodiments, the plurality of semiconductor devices is located(712) on the substrate below the one or more mask layers. In someembodiments, at least some of the plurality of semiconductor devices areat least partially embedded in the substrate.

In some embodiments, the substrate includes (714) a plurality oftransistors thereon and a semiconductor structure of the one or moresemiconductor structures is electrically coupled to a source or a drainof a transistor of the plurality of transistors (e.g., FIG. 6D).

In some embodiments, the substrate includes thereon (716) a plurality ofcomplementary metal-oxide semiconductor devices, including a p-typemetal-oxide-semiconductor transistor and an n-typemetal-oxide-semiconductor transistor (e.g., FIG. 6A).

In some embodiments, the method further includes electrically coupling(718) a first semiconductor structure of the one or more semiconductorstructures to a source or a drain of one of: the p-typemetal-oxide-semiconductor transistor or the n-typemetal-oxide-semiconductor transistor (e.g., FIG. 6D).

In some embodiments, a semiconductor structure of the one or moresemiconductor structures extends below a horizontal plane defined by abottom of a semiconductor device of the plurality of semiconductordevices (e.g., the semiconductor structure 608 extends below ahorizontal plane 618 defined by the bottom of a MOS transistor).

The method also includes forming (720) one or more filling layers overat least the first portion of the respective epitaxially grownsemiconductor structure (e.g., FIG. 6D).

In some embodiments, the method includes foregoing (722) removing atleast a portion of the respective epitaxially grown semiconductorstructure that is located above the height of the portion of the one ormore mask layers located adjacent to the first portion of the respectiveepitaxially grown semiconductor structure prior to forming the one ormore filling layers over at least the first portion of the respectiveepitaxially grown semiconductor structure.

In some embodiments, the one or more filling layers include (724) alayer of polysilicon.

In some embodiments, forming the one or more filling layers over atleast the first portion of the respective epitaxially grownsemiconductor structure includes forming (726) at least one continuousfilling layer over at least the first portion and the second portion ofthe respective epitaxially grown semiconductor structure and the portionof the one or more mask layers located adjacent to the first portion ofthe respective epitaxially grown semiconductor structure (e.g., FIG.3D).

In some embodiments, the one or more semiconductor structures have (728)crystalline structures and the one or more filling layers have amorphousand/or poly-crystalline structures (e.g., the one or more semiconductorstructures are crystalline germanium and the one or more filling layersare polysilicon).

The method further includes, subsequent to forming the one or morefilling layers over at least the first portion of the respectiveepitaxially grown semiconductor structure, removing (730) at least aportion of the respective epitaxially grown semiconductor structure thatis located above the height of the portion of the one or more masklayers located adjacent to the first portion of the respectiveepitaxially grown semiconductor structure (e.g., FIG. 3F).

In some embodiments, removing at least the portion of the respectiveepitaxially grown semiconductor structure includes planarizing (732) atleast the portion of the respective epitaxially grown semiconductorstructure.

In some embodiments, method also includes, subsequent to removing atleast the portion of the respective epitaxially grown semiconductorstructure, removing (736) at least a portion of the one or more masklayers (e.g., FIG. 3G).

In some embodiments, removing at least the portion of the one or moremask layers includes etching (738) at least the portion of the one ormore mask layers.

In some embodiments, removing at least the portion of the one or moremask layers includes etching (740) the entire one or more mask layers(e.g., FIG. 3G).

In some embodiments, the respective epitaxially grown semiconductorstructure has, before at least the portion of the respective epitaxiallygrown semiconductor structure that is located above the height of theportion of the one or more mask layers located adjacent to the firstportion of the respective epitaxially grown semiconductor structure isremoved, a first distance (e.g., the distance d₁ in FIG. 3D) to theportion of the one or more mask layers located adjacent to the firstportion of the respective epitaxially grown semiconductor structurealong a plane located at the height of the portion of the one or moremask layers located adjacent to the first portion of the respectiveepitaxially grown semiconductor structure. In some embodiments, therespective epitaxially grown semiconductor structure has, after at leastthe portion of the respective epitaxially grown semiconductor structurethat is located above the height of the portion of the one or more masklayers located adjacent to the first portion of the respectiveepitaxially grown semiconductor structure is removed, a second distance(e.g., the distance d₂ in FIG. 3F) to the portion of the one or moremask layers located adjacent to the first portion of the respectiveepitaxially grown semiconductor structure along the plane located at theheight of the portion of the one or more mask layers located adjacent tothe first portion of the respective epitaxially grown semiconductorstructure. The second distance is substantially identical to the firstdistance (e.g., the first distance is identical to the second distanceor the first distance is at least 90%, 95%, 99%, 99.5%, or 99.9% of thesecond distance).

In accordance with some embodiments, a semiconductor device (e.g., thesemiconductor device shown in FIG. 3F) includes a substrate (e.g., thesubstrate 102 in FIG. 3F) and one or more semiconductor layers (e.g.,the mask layer 104 in FIG. 3F) defining one or more regions that are notcovered by the one or more semiconductor layers over the substrate. Theone or more semiconductor layers include silicon. The semiconductordevice also includes one or more semiconductor structures (e.g., thesemiconductor structure 306 in FIG. 3F) located over the one or moreregions that are not covered by the one or more semiconductor layers.The one or more semiconductor structures includes germanium. Arespective semiconductor structure of the one or more semiconductorstructures includes a first portion located adjacent to the one or moresemiconductor layers and a second portion located away from the one ormore semiconductor layers. The first portion of the respectivesemiconductor structure has a height that is less than a height of aportion of the one or more semiconductor layers located adjacent to thefirst portion of the respective semiconductor structure (e.g., theportion of the semiconductor structure 306 in contact with the masklayer 104 has a height that is less than the height of the mask layer104). The second portion of the respective semiconductor structure has aheight that is equal to, or greater than, the height of the portion ofthe one or more semiconductor layers located adjacent to the firstportion of the respective semiconductor structure (e.g., the portion ofthe semiconductor structure 306 in the middle of the semiconductorstructure 306 has a height that is equal to the height of the mask layer104 as shown in FIG. 3F or a height that is greater than the height ofthe mask layer 104 as shown in FIG. 3E). The semiconductor devicefurther includes one or more filling layers located over at least thefirst portion of the respective semiconductor structure (e.g., thefilling layer 308 located over the portion of the semiconductorstructure 306 in contact with the mask layer 104).

In accordance with some embodiments, a semiconductor device (e.g., thesemiconductor device shown in FIG. 3G) includes a substrate (e.g., thesubstrate 102 in FIG. 3G) and one or more first semiconductor structures(e.g., the semiconductor structure 306 in FIG. 3G) located over thesubstrate. A respective first semiconductor structure of the one or morefirst semiconductor structures has a substantially flat top surface(e.g., the top surface has a flatness less than 100 nm), a substantiallyvertical side surface (e.g., the side surface and the substrate definean angle that is between 75° and 105°, and sometimes between 80° and100° or between 85° and 95°), and a diagonal surface extending from thetop surface to the side surface. The diagonal surface is non-paralleland non-perpendicular to the top surface and non-parallel andnon-perpendicular to the side surface (e.g., the diagonal surface andthe substrate form an angle that is less than the angle formed by theside surface and the substrate). The semiconductor device also includesone or more second semiconductor structures (e.g., portions of thefilling layer 308 in FIG. 3G). A respective second semiconductorstructure of the one or more second semiconductor structures is locatedon the diagonal surface of a corresponding first semiconductor structureof the one or more first semiconductor structures. The respective secondsemiconductor structure has a side surface aligned with the side surfaceof the corresponding first semiconductor structure and a top surfacealigned with the top surface of the corresponding first semiconductorstructure (e.g., the side surface of the filling layer 308 and the sidesurface of the semiconductor structure 306 are lined up and the topsurface of the filling layer 308 is level with the top surface of thesemiconductor structure 306).

The foregoing description, for purpose of explanation, has beendescribed with reference to specific embodiments. However, theillustrative discussions above are not intended to be exhaustive or tolimit the invention to the precise forms disclosed. Many modificationsand variations are possible in view of the above teachings. Theembodiments were chosen and described in order to best explain theprinciples of the invention and its practical applications, to therebyenable others skilled in the art to best utilize the invention andvarious embodiments with various modifications as are suited to theparticular use contemplated.

The following clauses also describe some of the embodiments.

Clause 1. A method for obtaining a semiconductor island, the methodcomprising:

epitaxially growing one or more semiconductor structures over asubstrate with one or more mask layers defining one or more regions thatare not covered by the one or more mask layers over the substrate,wherein the one or more semiconductor structures are epitaxially grownover the one or more regions that are not covered by the one or moremask layers, a respective epitaxially grown semiconductor structure ofthe one or more epitaxially grown semiconductor structures including afirst portion located adjacent to the one or more mask layers and asecond portion located away from the one or more mask layers, the firstportion of the respective epitaxially grown semiconductor structurehaving a height that is less than a height of a portion of the one ormore mask layers located adjacent to the first portion of the respectiveepitaxially grown semiconductor structure, the second portion of therespective epitaxially grown semiconductor structure having a heightthat is equal to, or greater than, the height of the portion of the oneor more mask layers located adjacent to the first portion of therespective epitaxially grown semiconductor structure;

forming one or more filling layers over at least the first portion ofthe respective epitaxially grown semiconductor structure; and,

subsequent to forming the one or more filling layers over at least thefirst portion of the respective epitaxially grown semiconductorstructure, removing at least a portion of the respective epitaxiallygrown semiconductor structure that is located above the height of theportion of the one or more mask layers located adjacent to the firstportion of the respective epitaxially grown semiconductor structure.

Clause 2. The method of clause 1, including:

foregoing removing at least a portion of the respective epitaxiallygrown semiconductor structure that is located above the height of theportion of the one or more mask layers located adjacent to the firstportion of the respective epitaxially grown semiconductor structureprior to forming the one or more filling layers over at least the firstportion of the respective epitaxially grown semiconductor structure.

Clause 3. The method of clause 1 or 2, wherein:

the one or more epitaxially grown semiconductor structures includegermanium.

Clause 4. The method of any of clauses 1-3, wherein:

the one or more mask layers include dielectric material.

Clause 5. The method of any of clauses 1-4, wherein:

the one or more filling layers include a layer of polysilicon.

Clause 6. The method of any of clauses 1-5, wherein:

forming the one or more filling layers over at least the first portionof the respective epitaxially grown semiconductor structure includesforming at least one continuous filling layer over at least the firstportion and the second portion of the respective epitaxially grownsemiconductor structure and the portion of the one or more mask layerslocated adjacent to the first portion of the respective epitaxiallygrown semiconductor structure.

Clause 7. The method of any of clauses 1-6, wherein the one or moresemiconductor structures are formed in a single epitaxial growthprocess.Clause 8. The method of any of clauses 1-7, wherein:

removing at least the portion of the respective epitaxially grownsemiconductor structure includes planarizing at least the portion of therespective epitaxially grown semiconductor structure.

Clause 9. The method of any of clauses 1-8, wherein the one or moresemiconductor structures have crystalline structures and the one or morefilling layers have amorphous and/or poly-crystalline structures.Clause 10. The method of any of clauses 1-9, further comprising:

subsequent to removing at least the portion of the respectiveepitaxially grown semiconductor structure, removing at least a portionof the one or more mask layers.

Clause 11. The method of clause 10, wherein removing at least theportion of the one or more mask layers includes etching at least theportion of the one or more mask layers.Clause 12. The method of clause 11, wherein removing at least theportion of the one or more mask layers includes etching the entire oneor more mask layers.Clause 13. The method of any of clauses 1-12, wherein the substrateincludes a plurality of semiconductor devices thereon.Clause 14. The method of clause 13, wherein the plurality ofsemiconductor devices is located on the substrate below the one or moremask layers.Clause 15. The method of clause 13 or 14, wherein the substrate includesa plurality of transistors thereon and a semiconductor structure of theone or more semiconductor structures is electrically coupled to a sourceor a drain of a transistor of the plurality of transistors.Clause 16. The method of any of clauses 13-15, wherein the substrateincludes thereon a plurality of complementary metal-oxide semiconductordevices, including a p-type metal-oxide-semiconductor transistor and ann-type metal-oxide-semiconductor transistor.Clause 17. The method of any of clauses 13-16, wherein:

a semiconductor structure of the one or more semiconductor structuresextends below a horizontal plane defined by a bottom of a semiconductordevice of the plurality of semiconductor devices.

Clause 18. The method of any of clauses 1-17, wherein:

the respective epitaxially grown semiconductor structure has, before atleast the portion of the respective epitaxially grown semiconductorstructure that is located above the height of the portion of the one ormore mask layers located adjacent to the first portion of the respectiveepitaxially grown semiconductor structure is removed, a first distanceto the portion of the one or more mask layers located adjacent to thefirst portion of the respective epitaxially grown semiconductorstructure along a plane located at the height of the portion of the oneor more mask layers located adjacent to the first portion of therespective epitaxially grown semiconductor structure; and

the respective epitaxially grown semiconductor structure has, after atleast the portion of the respective epitaxially grown semiconductorstructure that is located above the height of the portion of the one ormore mask layers located adjacent to the first portion of the respectiveepitaxially grown semiconductor structure is removed, a second distanceto the portion of the one or more mask layers located adjacent to thefirst portion of the respective epitaxially grown semiconductorstructure along the plane located at the height of the portion of theone or more mask layers located adjacent to the first portion of therespective epitaxially grown semiconductor structure, the seconddistance being substantially identical to the first distance.

Clause 19. A semiconductor device, comprising:

a substrate;

one or more semiconductor layers defining one or more regions that arenot covered by the one or more semiconductor layers over the substrate;

one or more semiconductor structures located over the one or moreregions that are not covered by the one or more semiconductor layers,the one or more semiconductor structures including germanium, arespective semiconductor structure of the one or more semiconductorstructures including a first portion located adjacent to the one or moresemiconductor layers and a second portion located away from the one ormore semiconductor layers, the first portion of the respectivesemiconductor structure having a height that is less than a height of aportion of the one or more semiconductor layers located adjacent to thefirst portion of the respective semiconductor structure, the secondportion of the respective semiconductor structure having a height thatis equal to, or greater than, the height of the portion of the one ormore semiconductor layers located adjacent to the first portion of therespective semiconductor structure; and

one or more filling layers located over at least the first portion ofthe respective semiconductor structure.

Clause 20. The semiconductor device of clause 19, wherein:

the second portion of the respective semiconductor structure has aheight that corresponds to the height of the portion of the one or moresemiconductor layers located adjacent to the first portion of therespective semiconductor structure.

Clause 21. The semiconductor device of clause 19 or 20, wherein:

the one or more semiconductor layers include dielectric material.

Clause 22. The semiconductor device of any of clauses 19-21, wherein:

the one or more semiconductor layers include silicon.

Clause 23. The semiconductor device of any of clauses 19-22, wherein:

the one or more filling layers include a layer of polysilicon.

Clause 24. The semiconductor device of any of clauses 19-23, wherein:

the one or more filling layers include at least one continuous fillinglayer located over at least (i) the first portion and the second portionof the respective semiconductor structure and (ii) the portion of theone or more semiconductor layers located adjacent to the first portionof the respective semiconductor structure.

Clause 25. The semiconductor device of any of clauses 19-24, wherein theone or more semiconductor structures are formed in a single epitaxialgrowth process.Clause 26. The semiconductor device of any of clauses 19-25, wherein theone or more semiconductor structures have crystalline structures and theone or more filling layers have amorphous and/or poly-crystallinestructures.Clause 27. The semiconductor device of any of clauses 19-26, wherein:

the one or more filling layers include at least one planarized surface.

Clause 28. The semiconductor device of any of clauses 19-27, wherein:

the one or more semiconductor layers have at least one planarizedsurface.

Clause 29. The semiconductor device of any of clauses 19-28, wherein:

the one or more semiconductor structures have at least one planarizedsurface.

Clause 30. The semiconductor device of any of clauses 19-29, wherein thesubstrate includes a plurality of semiconductor devices thereon.Clause 31. The semiconductor device of clause 30, wherein the pluralityof semiconductor devices is located on the substrate below the one ormore semiconductor layers.Clause 32. The semiconductor device of clause 30 or 31, wherein thesubstrate includes a plurality of transistors thereon and asemiconductor structure of the one or more semiconductor structures iselectrically coupled to a source or a drain of a transistor of theplurality of transistors.Clause 33. The semiconductor device of any of clauses 30-32, wherein thesubstrate includes thereon a plurality of complementary metal-oxidesemiconductor devices, including a p-type metal-oxide-semiconductortransistor and an n-type metal-oxide-semiconductor transistor.Clause 34. The semiconductor device of any of clauses 30-33, wherein:

a semiconductor structure of the one or more semiconductor structuresextends below a horizontal plane defined by a bottom of a semiconductordevice of the plurality of semiconductor devices.

Clause 35. The semiconductor device of any of clauses 19-34, wherein:

at least a portion of the one or more semiconductor layers, the firstportion of the one or more semiconductor structures, and a portion ofthe one or more filling layers define a single continuous planarizedsurface.

Clause 36. A semiconductor device, comprising:

a substrate;

one or more first semiconductor structures located over the substrate, arespective first semiconductor structure of the one or more firstsemiconductor structures having a substantially flat top surface, afirst substantially vertical side surface, and a first diagonal surfaceextending from the top surface to the first side surface, the firstdiagonal surface being non-parallel and non-perpendicular to the topsurface and non-parallel and non-perpendicular to the first sidesurface; and

one or more second semiconductor structures, a respective secondsemiconductor structure of the one or more second semiconductorstructures being located on the first diagonal surface of acorresponding first semiconductor structure of the one or more firstsemiconductor structures, the respective second semiconductor structurehaving a first side surface aligned with the first side surface of thecorresponding first semiconductor structure and a top surface alignedwith the top surface of the corresponding first semiconductor structure.

Clause 37. The semiconductor device of clause 36, wherein:

the respective first semiconductor structure has a second substantiallyvertical side surface that is distinct and separate from the first sidesurface, and a second diagonal surface that is distinct and separatefrom the first diagonal surface, the second diagonal surface extendingform the top surface to the second side surface;

the one or more second semiconductor structures include a secondsemiconductor structure located on the second diagonal surface of thecorresponding first semiconductor structure; and

the respective second semiconductor structure has a second side surfacealigned with the second side surface of the corresponding firstsemiconductor structure and a top surface aligned with the top surfaceof the corresponding first semiconductor structure.

Clause 38. The semiconductor device of clause 37, wherein:

the respective first semiconductor structure, the respective secondsemiconductor structure located on the first diagonal surface, and thesecond semiconductor structure located on the second diagonal surfacedefine a single continuous planarized surface.

Clause 39. The semiconductor device of any of clauses 36-38, furthercomprising:

one or more semiconductor layers.

Clause 40. The semiconductor device of clause 39, wherein:

the one or more semiconductor layers include dielectric material.

Clause 41. The semiconductor device of clause 39 or 40, wherein:

the one or more semiconductor layers include silicon.

Clause 42. The semiconductor device of any of clauses 39-41, wherein:

the one or more semiconductor layers have at least one planarizedsurface.

Clause 43. The semiconductor device of any of clauses 36-42, wherein:

the one or more second semiconductor structures include polysilicon.

Clause 44. The semiconductor device of any of clauses 36-43, wherein theone or more first semiconductor structures are formed in a singleepitaxial growth process.Clause 45. The semiconductor device of any of clauses 36-44, wherein theone or more first semiconductor structures have crystalline structuresand the one or more filling layers have amorphous and/orpoly-crystalline structures.Clause 46. The semiconductor device of any of clauses 36-45, wherein:

the one or more second semiconductor structures include at least oneplanarized surface.

Clause 47. The semiconductor device of any of clauses 36-46, wherein:

the one or more first semiconductor structures have at least oneplanarized surface.

Clause 48. The semiconductor device of any of clauses 36-47, wherein thesubstrate includes a plurality of semiconductor devices thereon.Clause 49. The semiconductor device of clause 48, wherein the pluralityof semiconductor devices is located on the substrate at a level belowthe one or more first semiconductor structures.Clause 50. The semiconductor device of clause 48 or 49, wherein thesubstrate includes a plurality of transistors thereon and a firstsemiconductor structure of the one or more first semiconductorstructures is electrically coupled to a source or a drain of atransistor of the plurality of transistors.Clause 51. The semiconductor device of any of clauses 48-50, wherein thesubstrate includes thereon a plurality of complementary metal-oxidesemiconductor devices, including a p-type metal-oxide-semiconductortransistor and an n-type metal-oxide-semiconductor transistor.Clause 52. The semiconductor device of any of clauses 48-51, wherein:

a first semiconductor structure of the one or more first semiconductorstructures extends below a horizontal plane defined by a bottom of asemiconductor device of the plurality of semiconductor devices.

What is claimed is:
 1. A method for obtaining a semiconductor island,the method comprising: epitaxially growing one or more semiconductorstructures over a substrate with one or more mask layers defining one ormore regions that are not covered by the one or more mask layers overthe substrate, wherein the one or more semiconductor structures areepitaxially grown over the one or more regions that are not covered bythe one or more mask layers, a respective epitaxially grownsemiconductor structure of the one or more epitaxially grownsemiconductor structures including a first portion located adjacent tothe one or more mask layers and a second portion located away from theone or more mask layers, the first portion of the respective epitaxiallygrown semiconductor structure having a height that is less than a heightof a portion of the one or more mask layers located adjacent to thefirst portion of the respective epitaxially grown semiconductorstructure, the second portion of the respective epitaxially grownsemiconductor structure having a height that is equal to, or greaterthan, the height of the portion of the one or more mask layers locatedadjacent to the first portion of the respective epitaxially grownsemiconductor structure; forming one or more filling layers over atleast the first portion of the respective epitaxially grownsemiconductor structure; and, subsequent to forming the one or morefilling layers over at least the first portion of the respectiveepitaxially grown semiconductor structure, removing at least a portionof the respective epitaxially grown semiconductor structure that islocated above the height of the portion of the one or more mask layerslocated adjacent to the first portion of the respective epitaxiallygrown semiconductor structure.
 2. The method of claim 1, including:foregoing removing at least a portion of the respective epitaxiallygrown semiconductor structure that is located above the height of theportion of the one or more mask layers located adjacent to the firstportion of the respective epitaxially grown semiconductor structureprior to forming the one or more filling layers over at least the firstportion of the respective epitaxially grown semiconductor structure. 3.The method of claim 1, wherein: the one or more epitaxially grownsemiconductor structures include germanium.
 4. The method of claim 1,wherein: the one or more mask layers include dielectric material.
 5. Themethod of claim 1, wherein: the one or more filling layers include alayer of polysilicon.
 6. The method of claim 1, wherein: forming the oneor more filling layers over at least the first portion of the respectiveepitaxially grown semiconductor structure includes forming at least onecontinuous filling layer over at least the first portion and the secondportion of the respective epitaxially grown semiconductor structure andthe portion of the one or more mask layers located adjacent to the firstportion of the respective epitaxially grown semiconductor structure. 7.The method of claim 1, wherein the one or more semiconductor structuresare formed in a single epitaxial growth process.
 8. The method of claim1, wherein: removing at least the portion of the respective epitaxiallygrown semiconductor structure includes planarizing at least the portionof the respective epitaxially grown semiconductor structure.
 9. Themethod of claim 1, wherein the one or more semiconductor structures havecrystalline structures and the one or more filling layers have amorphousand/or poly-crystalline structures.
 10. The method of claim 1, furthercomprising: subsequent to removing at least the portion of therespective epitaxially grown semiconductor structure, removing at leasta portion of the one or more mask layers.
 11. The method of claim 10,wherein removing at least the portion of the one or more mask layersincludes etching at least the portion of the one or more mask layers.12. The method of claim 11, wherein removing at least the portion of theone or more mask layers includes etching the entire one or more masklayers.
 13. The method of claim 1, wherein the substrate includes aplurality of semiconductor devices thereon.
 14. The method of claim 13,wherein the plurality of semiconductor devices is located on thesubstrate below the one or more mask layers.
 15. The method of claim 13,wherein the substrate includes a plurality of transistors thereon and asemiconductor structure of the one or more semiconductor structures iselectrically coupled to a source or a drain of a transistor of theplurality of transistors.
 16. The method of claim 13, wherein thesubstrate includes thereon a plurality of complementary metal-oxidesemiconductor devices, including a p-type metal-oxide-semiconductortransistor and an n-type metal-oxide-semiconductor transistor.
 17. Themethod of claim 13, wherein: a semiconductor structure of the one ormore semiconductor structures extends below a horizontal plane definedby a bottom of a semiconductor device of the plurality of semiconductordevices.
 18. The method of claim 1, wherein: the respective epitaxiallygrown semiconductor structure has, before at least the portion of therespective epitaxially grown semiconductor structure that is locatedabove the height of the portion of the one or more mask layers locatedadjacent to the first portion of the respective epitaxially grownsemiconductor structure is removed, a first distance to the portion ofthe one or more mask layers located adjacent to the first portion of therespective epitaxially grown semiconductor structure along a planelocated at the height of the portion of the one or more mask layerslocated adjacent to the first portion of the respective epitaxiallygrown semiconductor structure; and the respective epitaxially grownsemiconductor structure has, after at least the portion of therespective epitaxially grown semiconductor structure that is locatedabove the height of the portion of the one or more mask layers locatedadjacent to the first portion of the respective epitaxially grownsemiconductor structure is removed, a second distance to the portion ofthe one or more mask layers located adjacent to the first portion of therespective epitaxially grown semiconductor structure along the planelocated at the height of the portion of the one or more mask layerslocated adjacent to the first portion of the respective epitaxiallygrown semiconductor structure, the second distance being substantiallyidentical to the first distance.
 19. A semiconductor device, comprising:a substrate; one or more semiconductor layers defining one or moreregions that are not covered by the one or more semiconductor layersover the substrate, the one or more semiconductor layers includingsilicon; one or more semiconductor structures located over the one ormore regions that are not covered by the one or more semiconductorlayers, the one or more semiconductor structures including germanium, arespective semiconductor structure of the one or more semiconductorstructures including a first portion located adjacent to the one or moresemiconductor layers and a second portion located away from the one ormore semiconductor layers, the first portion of the respectivesemiconductor structure having a height that is less than a height of aportion of the one or more semiconductor layers located adjacent to thefirst portion of the respective semiconductor structure, the secondportion of the respective semiconductor structure having a height thatis equal to, or greater than, the height of the portion of the one ormore semiconductor layers located adjacent to the first portion of therespective semiconductor structure; and one or more filling layerslocated over at least the first portion of the respective semiconductorstructure.
 20. A semiconductor device, comprising: a substrate; one ormore first semiconductor structures located over the substrate, arespective first semiconductor structure of the one or more firstsemiconductor structures having a substantially flat top surface, asubstantially vertical side surface, and a diagonal surface extendingfrom the top surface to the side surface, the diagonal surface beingnon-parallel and non-perpendicular to the top surface and non-paralleland non-perpendicular to the side surface; and one or more secondsemiconductor structures, a respective second semiconductor structure ofthe one or more second semiconductor structures being located on thediagonal surface of a corresponding first semiconductor structure of theone or more first semiconductor structures, the respective secondsemiconductor structure having a side surface aligned with the sidesurface of the corresponding first semiconductor structure and a topsurface aligned with the top surface of the corresponding firstsemiconductor structure.